IJSRP, Volume 2, Issue 7, July 2012 Edition

Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. A typical processor devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given to the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. This paper presents the design of a low power high speed algorithms for arithmetic logic units using this ancient mathematics techniques and also their hardware implementation. Even convolution algorithms using this technique are discussed along with their FGPA implementation. Employing these techniques in the computation algorithms of the coprocessor has reduced the complexity, execution time, area, power. Further research prospects may include the design and development of a Vedic DSP chip using VLSI technology.